There is a growing need to lower the operating voltage of logic circuits, for example in order to reduce power consumption. This can be achieved by not stacking differential pairs in a logic circuit. U.S. Pat. No. 5,751,169 describes such a circuit where a first differential pair provides an amplified level-shifted output in response to a first differential input and a second differential pair provides an amplified output in response to a second differential input, these two outputs providing “exclusionary” signals processed by a comparator stage. Using such single stacks of differential pairs of transistors enables to reduce the necessary operative voltage. Nevertheless, in that patent, the “exclusionary” signals are not symmetric because of the level shift in the first pair. As a result, the operating speed of the logic circuit is limited since the comparator stage is not controlled in a differential mode.